The principal investigators at the University of Virginia will develop a community resource toolset for early design stage thermal modeling of VLSI designs. Thermal limits are widely cited by industry as a severe limit on future VLSI design capabilities. Efforts to reduce scale, increase transistors and functionality increase thermal loads while increasing power leakage, faults, and electrical usage. This project will develop tools for the pre-RTL design stage where there is the greatest opportunity to address space and time characteristics of computation, packaging and cooling choices and interactions with other components. Users will be able to model full systems; tools will be validated, allow for flexible connections with each other as well as system simulators; and they will support rapid learning. The tools will enable a broad research and education community to participate in power-aware architecture studies. The tools will build on Virginia's existing chip modeling capabilities. Broader impacts include providing new research and education infrastructure to a wide community or researchers and educators, supporting the education and training of engineers who can solve these pressing problems in industry, and an outreach program for women, minorities, and high school students.
CRI: Comprehensive, Pre-RTL Architectural Thermal Modeling